Current Issue : July-September Volume : 2026 Issue Number : 3 Articles : 5 Articles
The actual implementation of fifth-generation (5G) and beyond networks faces persistent challenges, including environmental interference and limited coverage, which compromise transmission stability and network feasibility. Reconfigurable Intelligent Surfaces (RISs) have emerged as a promising technology to dynamically reconfigure wireless propagation environments and enhance communication quality. To fully unlock the potential of RIS, this paper proposes a novel deployment strategy based on Double Deep Q-Networks (DDQNs) that jointly optimizes the RIS placement and phase shift configuration to maximize the system sum-rate. Specifically, the coverage area is discretized into a grid, and at each candidate location, a DDQN-based method is developed to solve the corresponding non-convex phase optimization problem. Simulation results reveal that our proposed strategy signicantly surpasses conventional benchmark schemes, resulting in a sum-rate improvement of up to 38.41%. The study provides a practical and efficient predeployment framework for RIS-enhanced wireless networks....
Ensuring security and processing speed are crucial attributes in today's computing applications. One of the most commonly used encryption systems is the Rivest–Shamir–Adleman (RSA), whose strength lies in the difficulty of breaking its keys. However, to continue guaranteeing adequate levels of protection, the size of these keys tends to grow over time, resulting in more complex encryption/decryption processes and longer operating times. This paper describes an RSA cryptographic accelerator soft- core as an alternative to state- of- the- art implementations solely based on efficient Montgomery modular executions. The proposed solution utilizes compression- based modular multipliers to handle the complexity of the modular- exponentiation operations. Furthermore, we further enhance performance by introducing a pseudomodulo strategy for processing the information in more efficient hardware (i.e., 2n −1) and then correcting the results back to the original modulo 2n + k. The system was implemented using the MAX 10 10M50DAF484C7G FPGA and was integrated into a NEORV32 RISC- V core. Results show that the new compression- based multipliers, particularly with the use of pseudomoduli, provide significantly higher gains in terms of delay, delay × logic elements, and execution time than approaches based on direct modulo multiplication and with the state of the art based on Montgomery multiplication....
Recent advances in artificial intelligence have made power efficiency a primary objective in system design. In this context, stochastic computing (SC), which processes probabilistic bitstreams using simple logic, and spiking neural networks (SNNs), a neuromorphic paradigm, have gained prominence as alternative approaches. This study proposes a Stochastic Computing Neural Network (SC-NN) framework that minimizes the intrinsic errors of stochastic computing and leverages the isomorphism between one-count operations on bitstreams and spike-rate computations in spiking neural networks, yielding improvements in accuracy and hardware efficiency. In contrast to earlier studies that utilized independent random number sequences of 10 bits or higher, our study employed a practically implementable 8-bit linear feedback shift Register (LFSR)-based pseudo-random bitstream. Using 4 taps and 255 seeds improves the realism of the hardware. Despite the inherent accuracy ceiling of pseudo-random sequences, the proposed method achieves higher accuracy. Applied to an 8-bit SC-based neural network accelerator, the proposed design improves accuracy by 35% over a conventional FSM baseline, while reducing power and area by 43.8% and 17.2%, respectively, and decreasing delay by 5.5%. These improvements translate to a 2.3× enhancement in the Figure of Merit (FoM), which was further verified through physical layout and FPGA results. Overall, this work introduces a new paradigm that enables simultaneous gains in accuracy and efficiency for low-power AI by suppressing the error sources and embedding the structural similarity between SNNs and SC into the design....
The network traffic of 3D parallel training in large-scale deep learning, featuring burstiness, hot-spots, and periodic large-bandwidth patterns, severely challenges network efficiency, necessitating a high-performance and flexible optical network solution. To address this, this paper proposes Mercury, a hybrid optical network based on physical optical components: its optical timeslot switching (OTS) subnet uses an arrayed waveguide grating router (AWGR) and tunable lasers for dynamic traffic, while the optical circuit switching (OCS) subnet relies on wavelength selective switches (WSSs) for low-latency high-bandwidth transmission, which is coordinated by selective valiant load balancing (S-VLB) and most efficient path configuration (MEPC) mechanisms. Validated via simulations and FPGA-based testbed experiments, Mercury outperforms the Sirius network by reducing epoch training time (e.g., 179s with five jobs) and relieving OTS congestion through offloading large flows to OCS. This work demonstrates that Mercury provides a flexible, high-performance physical optical solution for 3D parallel training of large-scale deep learning models....
This work describes the development of the Multi-channel Integrated Zone-sampling Analogue-memory based Readout (MIZAR) ASIC. This 64-channel chip was designed as part of NASA’s POEMMA Balloon with RADIO (PBR) mission, which aims to detect Ultra-High-Energy Cosmic Rays (UHECRs) and τ showers produced by the interaction of Cosmic Neutrinos (CNs) in the crust. The ASIC was implemented to read out a tile of 8 × 8 Silicon Photomultipliers (SiPMs) used to acquire the optical Cherenkov signals generated by Extensive Air Showers (EASs). A channel is partitioned into 256 cells where each one integrates an analogue memory, aWilkinson Analog-to-Digital Converter (ADC) and a digital memory operating at the nominal sampling rate of 200 MS/s (with a 5 ns integration time). The signal is digitized on-chip, then the converted data is read out by an FPGA. The MIZAR also provides a 64-bit hitmap as a first-level trigger which can be elaborated by an external firmware. This ASIC can also be configured to further segment the channels into units of 32 or 64 cells each and the ADC resolution can be set to a range between 8 and 12 bits. The chip was designed in a commercial 65 nm CMOS technology node and it was submitted for production in December 2024. The ASICs were delivered in March 2025....
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